EDI8L32256C 256kx32 sram module 1 EDI8L32256C rev. 4 3/98 eco#9662 features 256kx32, 5v static ram the EDI8L32256C is a high speed, 5v, 8 megabit sram. the device is available with access times of 15, 17, 20 and 25ns, allowing the creation of a no wait state dsp memory solution. the device can be configured as a 256kx32 and used to create a single chip external data memory solution for texas instruments' tms320c30/31, tms 320c32 or tms320c4x, motorola's dsp96002 and analog device's sharc tm dsp. alternatively the device's chip enables can be used to configure it as a 512kx16. a 512kx48 program memory array for analog's sharc tm dsp is created using three devices. if this memory is too deep, two 256kx24s (edi8l24256c) can be used to create a 256kx48 array or two 128kx24s (edi8l24128c) can be used to create a 128kx48 array. the device provides a 32% space savings when compared to two monolithic 256kx16, 44 pin sojs. the device provides a memory upgrade of the edi8l32128c (128kx32) and the edi8l3265c (64kx32). for more memory the device can be upgraded to the edi8l32512c (512kx32). 256kx32 bit cmos static dsp memory solution ? texas instruments tms320c3x, tms320c4x ? analog sharc tm dsp ? motorola dsp96002 random access memory array ? fast access times: 15, 17, 20 and 25ns ? individual byte enables ? user configurable organization with minimal additional logic ? master output enable and write control ? ttl compatible inputs and outputs ? fully static, no clocks surface mount package ? 68 lead plcc, no. 99, jedec mo-47ae ? small footprint, 0.990 sq. in. ? multiple ground pins for maximum noise immunity single +5v (5%) supply operation pin names a?-a17 address inputs e?-e1 chip enables (one per word) bs?-bs3 byte selects (one per byte) w master write enable g master output enable dq?-dq31 common data input/output vcc power (+5v5%) vss ground nc no connection a -a17 g w e e1 bs bs1 bs2 bs3 18 256kx32 memory array dq -dq7 dq8-dq15 dq16-dq23 dq24-dq31 electronic designs incorporated ? one research drive ? westborough, ma 01581usa ? 508-366-5151 ? fax 508-836-4850 ? http://www.electronic-designs.com pin configurations and block diagram note: solder reflow temperature should not exceed 260c for 10 seconds. 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 dq17 dq18 dq19 vss dq20 dq21 dq22 dq23 vcc dq24 dq25 dq26 dq27 vss dq28 dq29 dq30 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 dq14 dq13 dq12 vss dq11 dq10 dq9 dq8 vcc dq7 dq6 dq5 dq4 vss dq3 dq2 dq1 dq31 27 a6 28 a5 29 a4 30 a3 31 a2 32 a1 33 a? 34 vcc 35 a13 36 a12 37 a11 38 a10 39 a9 40 a8 41 a7 42 dq? 43 9 dq16 8nc 7a17 6 bs3\ 5 bs2\ 4 bs1\ 3 bs?\ 2e1\ 1vcc 68 nc 67 e?\ 66 g\ 65 w\ 64 a16 63 a15 62 a14 61 dq15 note: for memory upgrade information refer to page 8, figure 8 "edi mcm-l upgrade path".
2 EDI8L32256C rev. 4 3/98 eco#9662 EDI8L32256C 256kx32 sram module absolute maximum ratings* recommended dc operating conditions parameter sym min typ max units supply voltage vcc 4.75 5.0 5.25 v supply voltage vss 0 0 0 v input high voltage vih 2.2 -- vcc+0.5 v input low voltage vil -0.3 -- 0.8 v voltage on any pin relative to vss -0.5v to 7.0v operating temperature ta (ambient) commercial 0c to + 70c industrial -40c to +85c storage temperature -55c to +125c power dissipation 3.1 watts output current. 20 ma junction temperature, tj 175c dc electrical characteristics parameter sym conditions min max units 15/17 20/25 operating power supply current icc1 w= vil, ii/o = 0ma, 575 480 ma min cycle standby (ttl) supply current icc2 e 3 vih, vin vil or 120 120 ma vin 3 vih, f=?mhz full standbysupply current icc3 e 3 vcc-0.2v 20 20 ma vin 3 vcc-0.2v or vin 0.2v input leakage current ili vin = 0v to vcc 10 a output leakage current ilo v i/o = 0v to vcc 10 a output high volltage voh ioh = -4.0ma 2.4 v output low voltage vol iol = 8.0ma 0.4 v capacitance truth table (f=1.0mhz, vin=vcc or vss) parameter sym max unit address lines ca 20 pf data lines cd/q 10 pf write & output enable lines w, g 6 pf chip enable lines/byte select e, bs 9 pf figure 1 figure 2 255 vcc 5 pf 480 q 255 vcc 30 pf 480 q ac test conditions (note: for tehqz,tghqz and twlqz, cl = 5pf) input pulse levels vss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load figure 1 e w g bs?-3 mode output power h x x x standby high z icc2,icc3, l h h x output disable high z icc1 l x x h output disable high z icc1 l h l l read dout icc1 l l x l write din icc1 x means don't care *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.
EDI8L32256C 256kx32 sram module 3 EDI8L32256C rev. 4 3/98 eco#9662 ac characteristics read cycle symbol 15ns 17ns 20ns 25ns parameter jedec alt. min max min max min max min max units read cycle time tavav trc 15 17 20 25 ns address access time tavqv taa 15 17 20 25 ns chip enable access time telqv tacs 15 17 20 25 ns byte select access time tblqx tblz 15 17 20 25 ns chip enable to output in low z (1) telqx tclz 3 3 3 3 ns byte select to output in low z tblqx tblz 3 3 3 3 ns chip disable to output in high z (1) tehqz tchz 8 8 10 10 ns byte select to output in high z tbhqz tbhz 8 8 10 10 ns output hold from address change tavqx toh 3 3 3 3 ns output enable to output valid tglqv toe 6 8 10 10 ns output enable to output in low z (1) tglqx tolz 2 2 2 2 ns output disable to output in high z(1) tghqz tohz 5 6 8 10 ns read cycle 2 - w high read cycle 1 - w high, g, e low tavav tavqv tavqx data 2 a q address 1 address 2 data 1 tghqz telqv telqx e g q tehqz a tavav tglqv tglqx tavqv bsx ,
4 EDI8L32256C rev. 4 3/98 eco#9662 EDI8L32256C 256kx32 sram module ac characteristics write cycle note 1: parameter guaranteed, but not tested. write cycle 1 - w controlled symbol 15ns 17ns 20ns 25ns parameter jedec alt. min max min max min max min max units write cycle time tavav twc 15 17 20 25 ns chip enable to end of write telwh tcw 9 10 15 20 ns teleh tcw 9 10 15 20 ns byte select to end of write tblwh tbw 9 10 15 20 ns address setup time tavwl tas 0 0 0 0 ns tavel tas 0 0 0 0 ns address valid to end of write tavwh taw 10 12 15 15 ns taveh taw 10 12 15 15 ns write pulse width twlwh twp 10 12 15 15 ns twleh twp 10 12 15 15 ns write recovery time twhax twr 0 0 0 0 ns tehax twr 0 0 0 0 ns data hold time twhdx tdh 0 0 0 0 ns tehdx tdh 0 0 0 0 ns write to output in high z (1) twlqz twhz 060707010ns data to write time tdvwh tdw 6 8 8 12 ns tdveh tdw 6 8 8 12 ns output active from end of write (1) twhqx twlz 2 2 2 2 ns a e w d q tavav telwh tavwh twlwh tavwl tdvwh twhdx twhqx high z twlqz data valid twhax bsx ,
EDI8L32256C 256kx32 sram module 5 EDI8L32256C rev. 4 3/98 eco#9662 write cycle 2 - e controlled ordering information commercial (0c to 70c) industrial (-40c to +85c) part number speed package (ns) no. EDI8L32256C15ac 15 99 EDI8L32256C17ac 17 99 EDI8L32256C20ac 20 99 EDI8L32256C25ac 25 99 part number speed package (ns) no. EDI8L32256C17ai 17 99 EDI8L32256C20ai 20 99 EDI8L32256C25ai 25 99 a w e d q tavav tavel tehax tdveh tehdx teleh taveh data valid high z twleh bsx , package no. 99 68 lead plcc jedec mo-47ae weight = 4.2g theta j a = 40 c/w theta j c = 15 c/w package description 0.956 max 0.180 max 0.115 max 0.040 max 0.050 bsc 0.020 0.015 0.995 max 0.930 0.890 0.956 max 0.995 max electronic designs incorporated ? one research drive ? westborough, ma 01581usa ? 508-366-5151 ? fax 508-836-4850 ? http://www.electronic-designs.com electronic designs inc. reserves the right to change specifications without notice. cage no. 66301
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